Logo
Explore Help
Register Sign In
admin/1Cat-vLLM
Watch 1
Star 0 Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
1fc973c0b53a151bba062576cc3ff489cc1ceeec
1Cat-vLLM/tests/basic_correctness
T
History
Roger WangandVarun Sundar Rabindranath 1fc973c0b5 [V1][Core] Fix memory issue with logits & sampling (#14508)
Signed-off-by: Roger Wang <ywang@roblox.com>
Co-authored-by: Varun Sundar Rabindranath <3337719+varun-sundar-rabindranath@users.noreply.github.com>
2025-03-11 04:03:41 +00:00
..
__init__.py
…
test_basic_correctness.py
[misc] Rename Ray ADAG to Compiled Graph (#13928)
2025-02-26 20:03:28 -08:00
test_chunked_prefill.py
[misc] Rename Ray ADAG to Compiled Graph (#13928)
2025-02-26 20:03:28 -08:00
test_cpu_offload.py
Consolidate Llama model usage in tests (#13094)
2025-02-13 22:18:03 -08:00
test_cumem.py
[V1][Core] Fix memory issue with logits & sampling (#14508)
2025-03-11 04:03:41 +00:00
test_preemption.py
[1/n][CI] Load models in CI from S3 instead of HF (#13205)
2025-02-19 07:34:59 +00:00
Powered by Gitea Version: 28.3.0 Page: 4201ms Template: 197ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API